1. Field of the Invention
The present invention generally relates to semiconductor substrate processing systems. More specifically, the present invention relates to controlling accuracy and repeatability of etch processes in a semiconductor substrate processing system.
2. Description of the Related Art
To increase operational speed, devices (e.g., transistors, capacitors, and the like) in integrated microelectronic circuits have become ever smaller. One method for fabricating such devices comprises forming a patterned mask (e.g., photoresist mask) on a material layer disposed beneath such a mask (i.e., on an underlying layer) and then etching the material layer using the patterned photoresist mask as an etch mask. The etch mask generally is a replica of the structure to be formed (i.e., etched) in the underlying layer (or layers). As such, the etch mask has the same topographic dimensions as the structures being formed in the underlying layer(s).
Manufacturing variables of an etch process may result in a broad statistical distribution (i.e., large σ (sigma), where σ is a standard deviation) for the dimensions of the structures formed within a group (i.e., batch or lot) of wafers being etched. One method of controlling accuracy and repeatability for an etch process comprises measuring the smallest widths of elements of etch masks and formed structures, such as lines, columns, openings, spaces between the lines, and the like. Such smallest widths are known as “critical dimensions”, or CDs. In advanced ultra large scale integrated (ULSI) circuits, the critical dimensions are generally sub-micron dimensions of about 20 to 200 nm.
Parameters of the etch process recipe are generally selected using statistically generated results of critical dimension measurements for the patterned photoresist masks formed on wafers to be etched. After the etch process, the patterned photoresist masks are removed along with post-etch residues, the dimensions of the etched structures are measured and averaged, and the results are used to adjust subsequent etch process recipes. Conventionally, photoresist masks and post-etch residues are removed using wet stripping processes. The wet stripping processes are performed ex-situ and, as such, there is a significant delay (e.g., 1–2 hours) for receiving corrective feedback for improving the accuracy and repeatability of etch processes subsequently performed.
Therefore, there is a need in the art for an improved method for controlling accuracy and repeatability of an etch process during fabrication of semiconductor devices in a semiconductor substrate processing system.